1 PC Architecture Book Series
1-1 Bus Specifications and Release Dates
1-2 Comparison of Bus Frequency, Bandwidth and Number of Slots
1-3 PCI Express Aggregate Throughput for Various Link Widths
2-1 PCI Express Non-Posted and Posted Transactions
2-2 PCI Express TLP Packet Types
2-3 PCI Express Aggregate Throughput for Various Link Widths
3-1 Ordered Set Types
3-2 Data Link Layer Packet (DLLP) Types
3-3 PCI Express Address Space And Transaction Types
3-4 PCI Express Posted and Non-Posted Transactions
3-5 PCI Express TLP Variants And Routing Options
3-6 TLP Header Type and Format Field Encodings
3-7 Message Request Header Type Field Usage
3-8 Results Of Reading The BAR after Writing All "1s" To It
3-9 Results Of Reading The BAR Pair after Writing All "1s" To Both
3-10 Results Of Reading The IO BAR after Writing All "1s" To It
3-11 6 GB, 64-Bit Prefetchable Base/Limit Register Setup
3-12 2MB, 32-Bit Non-Prefetchable Base/Limit Register Setup
3-13 256 Byte IO Base/Limit Register Setup
4-1 PCI Express Address Space And Transaction Types
4-2 TLP Header Type Field Defines Transaction Variant
4-3 TLP Header Type Field Defines Transaction Variant
4-4 Generic Header Field Summary
4-5 TLP Header Type and Format Field Encodings
4-6 IO Request Header Fields
4-7 4DW Memory Request Header Fields
4-8 Configuration Request Header Fields
4-9 Completion Header Fields
4-10 Message Request Header Fields
4-11 INTx Interrupt Signaling Message Coding
4-12 Power Management Message Coding
4-13 Error Message Coding
4-14 Unlock Message Coding
4-15 Slot Power Limit Message Coding
4-16 Hot Plug Message Coding
4-17 DLLP Packet Types
4-18 Ack or Nak DLLP Fields
4-19 Power Management DLLP Fields
4-20 Flow Control DLLP Fields
4-21 Vendor-Specific DLLP Fields
5-1 Ack or Nak DLLP Fields
6-1 Example TC to VC Mappings
7-1 Required Minimum Flow Control Advertisements
8-1 Transactions That Can Be Reordered Due to Relaxed Ordering
8-2 Fundamental Ordering Rules Based on Strong Ordering and RO Attribute
8-3 Weak Ordering Rules Enhance Performance
8-4 Ordering Rules with Deadlock Avoidance Rules
9-1 Format and Usage of Message Control Register
9-2 INTx Message Codes
10-1 Error Message Codes and Description
10-2 Completion Code and Description
10-3 Error-Related Command Register Bits
10-4 Description of PCI-Compatible Status Register Bits for Reporting Errors
10-5 Default Classification of Errors
10-6 Transaction Layer Errors That are Logged
11-1 5-bit to 6-bit Encode Table for Data Characters
11-2 5-bit to 6-bit Encode Table for Control Characters
11-3 3-bit to 4-bit Encode Table for Data Characters
11-4 3-bit to 4-bit Encode Table for Control Characters
11-5 Control Character Encoding and Definition
12-1 Output Driver Characteristics
12-2 Input Receiver Characteristics
14-1 Summary of TS1 and TS2 Ordered-Set Contents
15-1 Maximum Power Consumption for System Board Expansion Slots
16-1 Major Software/Hardware Elements Involved In PC PM
16-2 System PM States as Defined by the OnNow Design Initiative
16-3 OnNow Definition of Device-Level PM States
16-4 Concise Description of OnNow Device PM States
16-5 Default Device Class PM States
16-6 D0 Power Management Policies
16-7 D1 Power Management Policies
16-8 D2 Power Management Policies
16-9 D3hot Power Management Policies
16-10 D3cold Power Management Policies
16-11 Description of Function State Transitions
16-12 Function State Transition Delays
16-13 The PMC Register Bit Assignments
16-14 PM Control/Status Register (PMCSR) Bit Assignments
16-15 Data Register Interpretation
16-16 Relationship Between Device and Link Power States
16-17 Link Power State Characteristics
16-18 Active State Power Management Control Field Definition
17-1 Introduction to Major Hot-Plug Software Elements
17-2 Major Hot-Plug Hardware Elements
17-3 Behavior and Meaning of the Slot Attention Indicator
17-4 Behavior and Meaning of the Power Indicator
17-5 Slot Capability Register Fields and Descriptions
17-6 Slot Control Register Fields and Descriptions
17-7 Slot Status Register Fields and Descriptions
17-8 The Primitives
18-1 PCI Express Connector Pinout
18-2 PCI Express Connector Auxiliary Signals
18-3 Power Supply Requirements
18-4 Add-in Card Power Dissipation
18-5 Card Interoperability
20-1 Enhanced Configuration Mechanism Memory-Mapped IO Address Range
21-1 Capability Register's Device/Port Type Field Encoding
22-1 Defined Class Codes
22-2 BIST Register Bit Assignment
22-3 Currently-Assigned Capability IDs
22-4 Command Register
22-5 Status Register
22-6 Bridge Command Register Bit Assignment
22-7 Bridge Control Register Bit Assignment
22-8 Bridge Primary Side Status Register
22-9 Bridge Secondary Side Status Register
22-10 AGP Status Register (Offset CAP_PTR + 4)
22-11 AGP Command Register (Offset CAP_PTR + 8)
22-12 Basic Format of VPD Data Structure
22-13 Format of the Identifier String Tag
22-14 Format of the VPD-R Descriptor
22-15 General Format of a Read or a Read/Write Keyword Entry
22-16 List of Read-Only VPD Keywords
22-17 Extended Capability (CP) Keyword Format
22-18 Format of Checksum Keyword
22-19 Format of the VPD-W Descriptor
22-20 List of Read/Write VPD Keywords
22-21 Example VPD List
22-22 Slot Numbering Register Set
22-23 Expansion Slot Register Bit Assignment
23-1 PCI Expansion ROM Header Format
23-2 PC-Compatible Processor/Architecture Data Area In ROM Header
23-3 PCI Expansion ROM Data Structure Format
24 - 1 PCI Express Capabilities Register
24 - 2 Device Capabilities Register (read-only)
24 - 3 Device Control Register (read/write)
24 - 4 Device Status Register
24 - 5 Link Capabilities Register
24 - 6 Link Control Register
24 - 7 Link Status Register
24 - 8 Slot Capabilities Register (all fields are HWInit)
24 - 9 Slot Control Register (all fields are RW)
24 - 10 Slot Status Register
24 - 11 Root Control Register (all fields are RW)
24 - 12 Root Status Register
24 - 13 Advanced Error Reporting Capability Register Set
24 - 14 Port VC Capability Register 1 (Read-Only)
24 - 15 Port VC Capability Register 2 (Read-Only)
24 - 16 Port VC Control Register (Read-Write)
24 - 17 Port VC Status Register (Read-Only)
24 - 18 VC Resource Capability Register
24 - 19 VC Resource Control Register (Read-Write)
24 - 20 VC Resource Status Register (Read-Only)
D-1 Defined Class Codes
D-2 Class Code 0 (PCI rev 1.0)
D-3 Class Code 1: Mass Storage Controllers
D-4 Class Code 2: Network Controllers
D-5 Class Code 3: Display Controllers
D-6 Class Code 4: Multimedia Devices
D-7 Class Code 5: Memory Controllers
D-8 Class Code 6: Bridge Devices
D-9 Class Code 7: Simple Communications Controllers
D-10 Class Code 8: Base System Peripherals
D-11 Class Code 9: Input Devices
D-12 Class Code A: Docking Stations
D-13 Class Code B: Processors
D-14 Class Code C: Serial Bus Controllers
D-15 Class Code D: Wireless Controllers
D-16 Class Code E: Intelligent IO Controllers
D-17 Class Code F: Satellite Communications Controllers
D-18 Class Code 10h: Encryption/Decryption Controllers
D-19 Class Code 11h: Data Acquisition and Signal Processing Controllers
D-20 Definition of IDE Programmer's Interface Byte Encoding
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